A Power and Energy Exploration of Network-on-Chip Architectures

Abstract

In this study, we analyse the move towards networks-on-chips from an energy perspective by accurately modelling a circuit-switched router, a wormhole router and a speculative virtual-channel router in a 90nm CMOS process. All the routers are shown to dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data-path. This leads to the key result that, if this trend continues, the energy cost of more elaborate control would not be vast, making it easier to justify. Given effective clock-gating, this additional energy is also shown to be more or less independent of network congestion. Accurate speed and area metrics are also reported for the networks, which would allow a more complete comparison to be made across the NoC architectural space considered