1998 · 87 citations · 16 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock GatingClock ManagementFinite-state MachinesLow-power Digital Circuit DesignPower ManagementPower OptimizationCircuit OptimizationClock Gating For Digital CircuitsClock Gating OptimizationFinite State Machine DesignLow-power Finite State MachinesPower Reduction AnalysisSwitching Activity AnalysisSwitching Activity Reduction
Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clock-gating technique based on finite state machine (FSM) decomposition. We compute two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. This way we will have a small amount of logic that is active most of the time, during which is disabling a much larger circuit, the other sub-FSM.
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