Concepedia

Cache Power Gating

Cache Power Gating is a low-power design technique that selectively disables the power supply to inactive cache blocks or subarrays using sleep transistors, thereby reducing static leakage energy without altering the cache's architectural functionality.

14

Publications

388

Citations

45

Authors

16

Institutions

Publications per year

2017–2026

1

Parents

Publications

14

A 45 nm 8-Core Enterprise Xeon¯ Processor

Stefan Rusu, Simon Tam, H. Muljono et al. · IEEE Journal of Solid-State Circuits · 2010 · 128 citations

, , +17

Run-time power-gating in caches of GPUs for leakage energy savings

Yue Wang, Soumyaroop Roy, N. Ranganathan · Design, Automation, and Test in Europe · 2012 · 37 citations

, , +17

A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications

Nathan Ickes, Daniel Finchelstein, Anantha P. Chandrakasan · 2008 · 35 citations

, , +17

Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems

Manish Arora, Srilatha Manne, Indrani Paul et al. · 2015 · 34 citations

, , +17

Power / Capacity Scaling

Mark Gottscho, Abbas BanaiyanMofrad, Nikil Dutt et al. · 2014 · 25 citations

, , +17

1–5 of 14

Authors

45

  1. HM
    H. Muljono

    Intel (United States), United States

    2 publications · 148 citations

    2

    h-index

  2. ND
    Nikil Dutt

    University of California, Irvine, United States

    2 publications · 39 citations

    2

    h-index

  3. SR
    Soumyaroop Roy

    University of South Florida, United States

    2 publications · 49 citations

    2

    h-index

  4. MR
    Matt Ratta

    Intel (United States), United States

    2 publications · 148 citations

    2

    h-index

  5. DM
    Dean M. Tullsen

    University of California San Diego, United States

    2 publications · 53 citations

    2

    h-index

1–5 of 45

Institutions

16

  1. Intel (United States)

    Santa Clara, United States

    4 h-index

    20 publications

    1.5K citations

  2. University of California, Los Angeles

    Los Angeles, United States

    3 h-index

    6 publications

    100 citations

  3. Advanced Micro Devices (United States)

    Sunnyvale, United States

    2 h-index

    4 publications

    57 citations

  4. University of California San Diego

    San Diego, United States

    2 h-index

    5 publications

    125 citations

  5. Advanced Micro Devices (Canada)

    Markham, Canada

    2 h-index

    5 publications

    173 citations

  6. University of South Florida

    Tampa, United States

    2 h-index

    4 publications

    98 citations

  7. Korea Advanced Institute of Science and Technology

    Daejeon, South Korea

    1 h-index

    2 publications

    20 citations

  8. Cavium (United States)

    San Jose, United States

    1 h-index

    1 publications

    34 citations

1–8 of 16

Venues

  1. IEEE Journal of Solid-State Circuits

    1 publications · 128 citations

    1

    h-index

  2. ACM Transactions on Architecture and Code Optimization

    TACO · 1 publications · 14 citations

    1

    h-index

  3. 1

    h-index

  4. Design, Automation, and Test in Europe

    Conference · 1 publications · 37 citations

    1

    h-index

1–4