Shishir Agrawal

A Physical Model for Fringe Capacitance in Double-Gate MOSFETs With Non-Abrupt Source/Drain Junctions and Gate Underlap

Shishir Agrawal, J.G. Fossum · IEEE Transactions on Electron Devices · 2010 · 23 citations

Device Modeling, Electrical Engineering, Dielectric Constant +13

On the Suitability of a High-$k$ Gate Dielectric in Nanoscale FinFET CMOS Technology

Shishir Agrawal, J.G. Fossum · IEEE Transactions on Electron Devices · 2008 · 16 citations

Engineering, Integrated Circuits, Silicon On Insulator +16

Insights on Design and Scalability of Thin-BOX FD/SOI CMOS

S. Chouksey, J.G. Fossum, Shishir Agrawal · IEEE Transactions on Electron Devices · 2010 · 16 citations

Low-power Electronics, Electrical Engineering, Thin-box Fd/soi Cmos +13

Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

S. Chouksey, J.G. Fossum, Ashkan Behnam et al. · IEEE Transactions on Electron Devices · 2009 · 12 citations

Device Modeling, Low-power Electronics, Electrical Engineering +14