N.S. Nagaraj

Benchmarks for interconnect parasitic resistance and capacitance

N.S. Nagaraj, T. Bonifield, Aishwarya Singh et al. · 2004 · 22 citations

3D Ic Architecture, Electrical Engineering, Physical Design (Electronics) +14

A 65 nm CMOS technology for mobile and digital signal processing applications

A. Chattedee, J. Yoon, Song Zhao et al. · 2005 · 22 citations

Low-power Electronics, Hardware Security, Electrical Engineering +14

Crosstalk noise verification in digital designs with interconnect process variations

N.S. Nagaraj, Poras T. Balsara, C. D. Cantrell · 2002 · 17 citations

Engineering, Vlsi Design, Analog Design +17

Chip hierarchical design system (CHDS)

R. G. Bushroe, S. Dasgupta, Aykut Dengi et al. · 1997 · 16 citations · Full text

Engineering, Electronic Design Automation, Electronic Design +20

Impact of interconnect technology scaling on SOC design methodologies

N.S. Nagaraj, W. R. Hunter, P.R. Chidambaram et al. · 2005 · 15 citations

System On Chip, Electrical Engineering, Accurate Rc Extraction +13