2005 · 22 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ScalingIntegrated Circuit DesignMemory DevicesStandard Cell DesignCmos Digital Circuit DesignCmos Logic CircuitsCmos Logic DesignCmos ScalingDigital Signal Processing FeaturesHigh PerformanceLogic Gate ImplementationMemory Circuit Design
This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm/sup 2/ and a SRAM memory density of 1.4 Mb/mm/sup 2/ using a sub-0.49 /spl mu/m/sup 2/ bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.
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