S.C. Chen

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chien‐Hao Chen, T.L. Lee, Tuo‐Hung Hou et al. · 2004 · 115 citations

Engineering, Electrical Engineering, Materials Science +14

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

Chung-Cheng Wu, Yuet‐Kin Leung, C. S. Chang et al. · 2003 · 46 citations

Engineering, Computer Engineering, Electrical Engineering +17

65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

S.K.H. Fung, H.T. Huang, Sheng-Jen Cheng et al. · 2004 · 45 citations · Full text

Engineering, Electrical Engineering, Low-power Design +13

A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

Shien-Yang Wu, J.J. Liaw, Chih‐Yung Lin et al. · Symposium on VLSI Technology · 2006 · 42 citations

Engineering, Computer Engineering, Electrical Engineering +17

Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide

Wei-Ting Wu, Bing‐Yue Tsui, Y.P. Huang et al. · IEEE Electron Device Letters · 2006 · 29 citations

Engineering, Electrical Engineering, Materials Science +17