P.-J. Sung - Concepedia

Author

P.-J. Sung

National Yang Ming Chiao Tung University

Also Known As

P. J. Sung, P. Sung, P.-J Sung, P.-J. Sung, P.J. Sung, Pei-Chieh Sung, Pin-Hsuan Sung, Ping-Hua Sung, Y.-C. Huang

Publications

348

Citations

H-Index

Concepts

All Affiliations

National Yang Ming Chiao Tung University National Cheng Kung University National Institutes of Applied Research Industrial Technology Research Institute Taiwan Semiconductor Manufacturing Company (Taiwan)

About

P.-J. Sung is an author at National Yang Ming Chiao Tung University specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	11	224
2	Electrical Engineering	11	11	224
3	Applied Physics	10	10	209
4	Materials Science	6	6	117
5	Natural Sciences	1	1	19

P.-J. Sung

Publications

257

Citations

H-Index

Page 1

	Year	Citations
A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing Y.-J. Lee, T.-C. Cho, Kuo-Hsing Kao, Semiconductor TechnologyElectrical EngineeringEngineeringNanoelectronicsElectronic Engineering	2014	41
Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO<inf>x</inf> on specific interfacial layers exhibiting 65% S.S. reduction and improved I<inf>ON</inf> C.-J. Su, Ying–Tsan Tang, Y.-C. Tsou, Sub XmlnsEngineeringGe NfinfetSemiconductor DeviceGe Interdiffusion	2017	31
Ge nanowire FETs with HfZrO<inf>x</inf> ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability Chun-Jun Su, T.-C. Hong, Y.-C. Tsou, Materials ScienceSemiconductorsElectrical EngineeringRoom TemperatureGe Nanowire	2017	19
A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node Ying–Tsan Tang, C.-J. Su, Yi‐Sheng Wang, Magnetic PropertiesDielectricsEngineeringPolymorphic Phase DistributionGate-oxide Granularity	2018	19
Study on the Roles of Charge Trapping and Fixed Charge on Subthreshold Characteristics of FeFETs Chengji Jin, C.-J. Su, Y. J. Lee, IEEE Transactions on Electron Devices Device ModelingMagnetismElectrical EngineeringCharge TrappingEngineering	2021	19
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using <i>In-Situ</i> ALD Digital O<sub>3</sub> Treatment Mu-Shih Yeh, Guang-Li Luo, Fu-Ju Hou, IEEE Journal of the Electron Devices Society Low-power ElectronicsElectrical EngineeringEngineeringGeo Desorption MechanismMicrofabrication	2018	18
First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT) Tu Hong, Wen-Hsin Chang, A. Agarwal, EngineeringHeterogeneous Complementary FetsIntegrated CircuitsInterconnect (Integrated Circuits)Semiconductor Device	2020	18
Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide Y.-J. Lee, S.-S. Chuang, C.-I. Liu, EngineeringMicrowave AnnealingSemiconductor DeviceSemiconductorsGe Cmos Manufacturing	2012	17
Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications P.-J. Sung, Chun‐Yen Chang, L.-Y. Chen, 3D Ic ArchitectureElectrical EngineeringEngineeringVlsi DesignAdvanced Packaging (Semiconductors)	2018	15
Determination of built-in-potential in N-I-P a-Si:H solar cells Minfang Han, P.-J. Sung, W.A. Anderson IEEE Electron Device Letters SemiconductorsSolar Physics (Heliophysics)Electrical EngineeringH Solar CellsAm1 Illumination	1982	14

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