C.-J. Su

A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel

Horng‐Chih Lin, Ming‐Hsien Lee, C.-J. Su et al. · IEEE Electron Device Letters · 2005 · 75 citations

Engineering, Nanocomputing, Flexible Sensor +20

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO<inf>x</inf> on specific interfacial layers exhibiting 65% S.S. reduction and improved I<inf>ON</inf>

C.-J. Su, Ying–Tsan Tang, Y.-C. Tsou et al. · 2017 · 31 citations

Sub Xmlns, Engineering, Ge Nfinfet +16

High-performance TFTs with Si nanowire channels enhanced by metal-induced lateral crystallization

C.-J. Su, Horng‐Chih Lin, T.Y. Huang · IEEE Electron Device Letters · 2006 · 30 citations

Engineering, Metal-induced Lateral Crystallization, New Device +16

Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

C.-J. Su, Horng‐Chih Lin, Hsinhan Tsai et al. · Nanotechnology · 2007 · 23 citations

Electrical Engineering, Thin-film Transistor, Engineering +11

A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node

Ying–Tsan Tang, C.-J. Su, Yi‐Sheng Wang et al. · 2018 · 19 citations

Magnetic Properties, Dielectrics, Engineering +21