C.-J. Su

A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel

Horng‐Chih Lin, Ming‐Hsien Lee, C.-J. Su et al. · IEEE Electron Device Letters · 2005 · 75 citations

Engineering, Electrical Engineering, Materials Science +14

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO<inf>x</inf> on specific interfacial layers exhibiting 65% S.S. reduction and improved I<inf>ON</inf>

C.-J. Su, Ying–Tsan Tang, Y.-C. Tsou et al. · 2017 · 31 citations

Engineering, Electrical Engineering, Materials Science +17

High-performance TFTs with Si nanowire channels enhanced by metal-induced lateral crystallization

C.-J. Su, Horng‐Chih Lin, T.Y. Huang · IEEE Electron Device Letters · 2006 · 30 citations

Engineering, Materials Engineering, Materials Science +17

Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

C.-J. Su, Horng‐Chih Lin, Hsinhan Tsai et al. · Nanotechnology · 2007 · 23 citations

Engineering, Electrical Engineering, Materials Science +17

Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using <i>In-Situ</i> ALD Digital O₃ Treatment

Mu-Shih Yeh, Guang-Li Luo, Fu-Ju Hou et al. · IEEE Journal of the Electron Devices Society · 2018 · 19 citations · Full text

Engineering, Electrical Engineering, Materials Science +17