Jianxin Lei

Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Atif Noori, Mihaela Balseanu, Pieter Boelen et al. · IEEE Transactions on Electron Devices · 2008 · 39 citations

Engineering, Vlsi Design, Integrated Circuits +18

High-k/metal gate stacks in gate first and replacement gate schemes

Sree Kesapragada, Rongjun Wang, Dave Liu et al. · 2010 · 17 citations

Materials Engineering, Materials Science, Electrical Engineering +14

Advantage of Siconi¿ Preclean over Wet Clean for Pre Salicide Applications Beyond 65nm Node

Jianxin Lei, See-Eng Phan, Xinliang Lu et al. · IEEE International Symposium on Semiconductor Manufacturing conference proceedings · 2006 · 15 citations

Engineering, Silicon On Insulator, Chemical Engineering +21

Extreme Contact Scaling with Advanced Metallization of Cobalt

Raymond Hung, Jin‐Hee Park, Tae Hong Ha et al. · 2018 · 14 citations

Engineering, Gapfill Material, Vacuum Device +18