J. Miyamoto - Concepedia

Author

J. Miyamoto

Toshiba (Japan)

Also Known As

J Miyamoto, J. Miyamoto, J.-I. Miyamoto, Junko MIYAMOTO, Junri Miyamoto, Miyamoto, J.

Publications

465

Citations

H-Index

Concepts

All Affiliations

Toshiba (Japan)

About

J. Miyamoto is an author at Toshiba (Japan) specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	11	257
2	Health Sciences	1	1	10
3	Natural Sciences	1	1	107
4	Applied Physics	1	1	10
5	Chemical Engineering	1	1	10

J. Miyamoto

Publications

310

Citations

H-Index

Page 1

	Year	Citations
CMS Physics : Technical Design Report Volume 1: Detector Performance and Software G.L. Bayatian, A. Korablev, A. Soha, CERN Document Server (European Organization for Nuclear Research) EngineeringRadiation DetectionPhysicsCms PhysicsDetector Performance	2006	107
Oxygen metabolism changes in patients with idiopathic normal pressure hydrocephalus before and after shunting operation J. Miyamoto, Kazunori Tatsuzawa, Yasuaki Inoue, Acta Neurologica Scandinavica	2007	29
A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed Jin‐Ki Kim, Koji Sakui, Sung-Soo Lee, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringEngineeringPage Sensing Time120-Mm/sup 2/	1997	26
A high-speed 64K CMOS RAM with bipolar sense amplifiers J. Miyamoto, S. Saito, H.S. Momose, IEEE Journal of Solid-State Circuits Electrical EngineeringChip SizeEngineeringVlsi DesignMixed-signal Integrated Circuit	1984	17
A new technique for measuring threshold voltage distribution in flash EEPROM devices T. Himeno, N. Matsukawa, H. Hazama, EngineeringMem TestingReliability EngineeringHigh Voltage EngineeringElectronic Packaging	2002	17
A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM K. Imamiya, Yoichi Iwata, Y. Sugiura, V-only 32Non-volatile MemoryElectrical EngineeringEngineeringVlsi Design	2002	16
A 1.0&amp;#181;m N-well CMOS/Bipolar technology for VLSI circuits J. Miyamoto, S. Saitoh, H.S. Momose, Electrical EngineeringEngineeringVlsi DesignCircuit SystemN-well Cmos/bipolar Technology	1983	15
1.0-&#181;m n-well CMOS/bipolar technology H.S. Momose, H. Shibata, S. Saitoh, IEEE Transactions on Electron Devices	1985	14
A 28ns CMOS SRAM with bipolar sense amplifiers J. Miyamoto, S. Saitoh, H.S. Momose, Electrical EngineeringBipolar DevicesCmos SramEngineeringMixed-signal Integrated Circuit	1984	14
An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell J. Miyamoto, J. Tsujimoto, N. Matsukawa, IEEE Journal of Solid-State Circuits Low-power ElectronicsNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design	1986	14

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