Koji Sakui

A CMOS bandgap reference circuit with sub-1-V operation

H. Banba, H. Shiga, Akira Umezawa et al. · IEEE Journal of Solid-State Circuits · 1999 · 874 citations

Low-power Electronics, Electrical Engineering, Engineering +11

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory

Tomoharu Tanaka, Yasunori Tanaka, Hiroki Nakamura et al. · IEEE Journal of Solid-State Circuits · 1994 · 85 citations

Non-volatile Memory, Shielded Bitline Architecture, Engineering +16

A reliable bi-polarity write/erase technology in flash EEPROMs

S. Aritome, R. Shirota, R. Kirisawa et al. · 2002 · 45 citations

Non-volatile Memory, Engineering, Emerging Memory Technology +17

A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories

Ken Takeuchi, S. Satoh, Tomoharu Tanaka et al. · IEEE Journal of Solid-State Circuits · 1999 · 34 citations

Non-volatile Memory, Electrical Engineering, Engineering +10

A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology

K. Imamiya, Y. Sugiura, Hiroshi Nakamura et al. · IEEE Journal of Solid-State Circuits · 1999 · 30 citations

Non-volatile Memory, Electrical Engineering, Engineering +12