S.W. Park

Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -

Ji Won Han, S.H. Park, Moonyoung Jeong et al. · 2023 · 60 citations

Third Dimension, Bit Density, Electrical Engineering +15

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node

Daewon Ha, Yunsung Lee, Seung‐Hwan Yoo et al. · 2024 · 21 citations

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch

Jaehyun Park, Juhun Park, Kyuman Hwang et al. · 2024 · 21 citations

Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F² Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

Daewon Ha, Wonsok Lee, M.H. Cho et al. · 2023 · 20 citations