J. Chilo - Concepedia

Author

J. Chilo

Institut de Microélectronique, Electromagnétisme et Photonique

Also Known As

Chilo, J., Chilo, Jean, J Chilo, J. CHILO, J. Chilo, Jean Chilo

Publications

398

Citations

H-Index

Concepts

All Affiliations

Institut de Microélectronique, Electromagnétisme et Photonique

About

J. Chilo is an author at Institut de Microélectronique, Electromagnétisme et Photonique specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	168
2	Electrical Engineering	8	8	168
3	Computer Engineering	5	5	104
4	Applied Physics	2	2	25
5	Mechanics	1	1	16

J. Chilo

Publications

273

Citations

H-Index

Page 1

	Year	Citations
Inductance and capacitance analytic formulas forVLSI interconnects Nicolas Delorme, Marie‐Pierre Belleville, J. Chilo Electronics Letters	1996	105
Coupling effects in the time domain for an interconnecting bus in high-speed GaAs logic circuits J. Chilo, Thierry Arnaud IEEE Transactions on Electron Devices Gaas TechnologyElectrical EngineeringEngineeringVlsi DesignHigh-frequency Device	1984	59
New skin-effect equivalent circuit T. Vu Dinh, B. Cabon, J. Chilo Electronics Letters Electrical EngineeringMicrostrip LineEngineeringCutaneous BiologyBioelectronics	1990	36
Time domain analysis of skin effect on lossy interconnections T. Vu Dinh, B. Cabon, J. Chilo Electronics Letters EngineeringWearable TechnologyInterconnect (Integrated Circuits)Electromagnetic CompatibilityWear Testing	1990	16
The inductive connection effects of a mounted SPDT in a plastic SO8 package Fabien Ndagijimana, J. Engdahl, A. Ahmadouche, Advanced PackagingElectrical EngineeringEngineeringAssembled So8 PackageAdvanced Packaging (Semiconductors)	2002	13
The inductive connection effects of a mounted SPDT in a plastic SO8 package Fabien Ndagijimana, J. Engdahl, A. Ahmadouche, Advanced PackagingElectrical EngineeringEngineeringAssembled So8 PackageAdvanced Packaging (Semiconductors)	2002	12
Proximity Effects of Interconnection Lines in High Speed Integrated Logic Circuits J. Chilo, G. Angénieux, C. Monllor Propagation MatricesEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits)	2006	11
Optimum computation of capacitance coefficients of multilevel interconnecting lines for advanced package A. Ahmadouche, J. Chilo IEEE Transactions on Components Hybrids and Manufacturing Technology EngineeringInterconnect (Integrated Circuits)Electromagnetic CompatibilityPhysical Design (Electronics)Advanced Packaging (Semiconductors)	1989	11
Frequency limitation on an assembled SO8 package Fabien Ndagijimana, J. Engdahl, A. Ahmadouche, Electrical EngineeringPhysical Design (Electronics)EngineeringAdvanced Packaging (Semiconductors)High-frequency Device	2002	10

Page 1