J.F. Lin

CMP process development for the via-middle 3D TSV applications at 28nm technology node

T.C. Tsai, W. C. Tsao, Welch Lin et al. · Microelectronic Engineering · 2011 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +11

Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER)

Yu‐Chi Yang, N. Breil, C. Y. Yang et al. · 2016 · 26 citations

Engineering, Electrical Engineering, Materials Science +13

Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

Wen‐Chin Lin, Jack Lin, T.C. Tsai et al. · Microelectronic Engineering · 2011 · 14 citations

Engineering, Electrical Engineering, Materials Science +16

Investigation of aluminum film properties and microstructure for replacement metal gate application

Rao Huang, T.C. Tsai, Welch Lin et al. · Microelectronic Engineering · 2013 · 10 citations

Natural Sciences, Materials Engineering, Materials Science +14