Ying Wu

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

Ying Wu, Mina Shahmohammadi, Yue Chen et al. · IEEE Journal of Solid-State Circuits · 2017 · 78 citations

Loop Bandwidth, Data Converter, Clock Recovery +6

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration

Ping Lu, Ying Wu, Pietro Andreani · IEEE Transactions on Circuits & Systems II Express Briefs · 2016 · 43 citations

Engineering, Measurement, Calibration +13

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

Ping Lu, Ying Wu, Pietro Andreani · 2012 · 16 citations

Improved Vernier Tdc, High-frequency Device, Mixed-signal Integrated Circuit +7

A Time-Domain 147fs_{rms 2.5}-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction

Ying Wu, Ping Lu, Robert Bogdan Staszewski · IEEE Transactions on Circuits and Systems I Regular Papers · 2020 · 15 citations · Full text

Engineering, Clock Recovery, Data Converter +13