Ping Lu

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

Ping Lu, Antonio Liscidini, Pietro Andreani · IEEE Journal of Solid-State Circuits · 2012 · 105 citations

Data Converter, Mixed-signal Integrated Circuit, Equivalent Resolution +7

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

Ying Wu, Mina Shahmohammadi, Yue Chen et al. · IEEE Journal of Solid-State Circuits · 2017 · 78 citations

Loop Bandwidth, Data Converter, Clock Recovery +6

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration

Ping Lu, Ying Wu, Pietro Andreani · IEEE Transactions on Circuits & Systems II Express Briefs · 2016 · 43 citations

Engineering, Measurement, Calibration +13

A 2-D GRO Vernier time-to-digital converter with large input range and small latency

Ping Lu, Antonio Liscidini, Pietro Andreani · Analog Integrated Circuits and Signal Processing · 2013 · 16 citations

Time-of-flight Camera, Large Input Range, Small Latency +2

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

Ping Lu, Ying Wu, Pietro Andreani · 2012 · 16 citations

Improved Vernier Tdc, High-frequency Device, Mixed-signal Integrated Circuit +7