A Time-Domain 147fs_{rms 2.5}-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction

Abstract

A 50 MS/s two-step flash-MASH 1-1-1 time-to-digital converter (TDC) employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology. Such an error-feedback unit of 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order noise-shaping TDC can be cascaded as a multi-stage noise shaping (MASH) configuration to achieve higher-order noise-shaping and, thereby high resolution. This paper also discusses different noise sources, linearity and noise tradeoffs in noise-shaping TDC and then demonstrates a histogram testing technique to correct the mismatch of 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> stage flash TDC. An on/off-chip delay modulation (DM) measurement technique is presented to characterize the TDC linearity and noise performance. Fabricated in 40-nm CMOS technology, the proposed TDC consumes 1.32 mW from a 1.1 V supply. At frequency below 2.5 MHz, the TDC error integrates to 147fsrms, which is equal to equivalent flash resolution of 1.6 ps.