S. Venkataraman

Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

Sybille Hellebrand, Janusz Rajski, Steffen Tarnick et al. · IEEE Transactions on Computers · 1995 · 405 citations

Engineering, Mem Testing, Verification +21

An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers

S. Venkataraman, Janusz Rajski, Sybille Hellebrand et al. · Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) · 2005 · 102 citations

Engineering, Vlsi Design, Pseudo-random Sequence +19

Poirot: applications of a logic fault diagnosis tool

S. Venkataraman, S.B. Drummonds · IEEE Design & Test of Computers · 2001 · 93 citations

Engineering, Verification, Diagnosis +19

An Experimental Study of N-Detect Scan ATPG Patterns on a Processor

S. Venkataraman, S. Sivaraj, Enamul Amyeen et al. · 2004 · 71 citations

Engineering, Computer Architecture, Test Data Generation +16

A technique for logic fault diagnosis of interconnect open defects

S. Venkataraman, S.B. Drummonds · 2002 · 67 citations

Fault Diagnosis, Engineering, Diagnosis +19