A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration

Qianqian Huang, Ru Huang, Zhan Zhan, +4

Striped Gate ConfigurationElectrical EngineeringSemiconductor DeviceEngineeringNanoelectronics +9

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

Chunlei Wu, Ru Huang, Qianqian Huang, +3

IEEE Transactions on Electron Devices

EngineeringChannel Surface PotentialSemiconductor DeviceTunneling MicroscopyNanoelectronics +14

Smart GaN platform: Performance & challenges

Chun-Lin Tsai, Yun-Hsiang Wang, Man Ho Kwan, +23

EngineeringEnergy EfficiencyGan Power DevicesPower Electronics ConverterPower Electronic Systems +14

A Novel Tunnel FET Design With Stacked Source Configuration for Average Subthreshold Swing Reduction

Chunlei Wu, Qianqian Huang, Yang Zhao, +3

IEEE Transactions on Electron Devices

Wide-bandgap SemiconductorElectrical EngineeringEngineeringNanoelectronicsBias Temperature Instability +7

Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

Qianqian Huang, Ru Huang, Chunlei Wu, +7

Comprehensive Performance Re-assessmentTfets PerformanceEngineeringVlsi DesignIntegrated Circuits +14

Hf_0.5Zr_0.5O₂-Based Ferroelectric Gate HEMTs With Large Threshold Voltage Tuning Range

Chunlei Wu, Hansheng Ye, Nikhita Shaju, +4

IEEE Electron Device Letters

SemiconductorsWide-bandgap SemiconductorElectrical EngineeringSemiconductor TechnologyEngineering +11

A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ Ratio

Yang Zhao, Chunlei Wu, Qianqian Huang, +8

IEEE Electron Device Letters

Wide-bandgap SemiconductorSemiconductor TechnologyElectrical EngineeringEngineeringFabricated Hs-tfets +12

CMOS-compatible GaN-on-Si field-effect transistors for high voltage power applications

Man Ho Kwan, King‐Yuen Wong, Y. S. Lin, +25

V Depletion-mode MisfetsElectrical EngineeringEngineeringNanoelectronicsV Enhancement-mode Fets +8

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Qianqian Huang, Rundong Jia, Cheng Chen, +13

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignCmos Baseline Technology +12

Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing

Jiadi Zhu, Yang Zhao, Qianqian Huang, +4

IEEE Electron Device Letters

Electrical EngineeringSemiconductor DeviceEngineeringTunneling MicroscopyPhysics +9