Smart GaN platform: Performance & challenges

Abstract

This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.