Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

Abstract

In this paper, a novel TFET design, called Pocket-mSTFET (PMS-TFET), is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from circuit design perspective, TFETs performance in terms of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated PMS-TFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> (~20μA/μm) and large I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ) at 0.6V. Largely alleviated super-linear onset issue, reduced Miller capacitance and delay, and much lower noise level were also experimentally obtained, as well as high effective gain. Circuit-level implementation based on PMS-TFET also shows significant improvement on energy efficiency and power reduction at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.