Shimpei Sato - Concepedia

Author

Shimpei Sato

Tokyo Institute of Technology ORCID

Also Known As

S. Sato, Sato, Shimpei, Shimpei SATO, Shimpei Sato

Publications

801

Citations

H-Index

Concepts

All Affiliations

Tokyo Institute of Technology National Institute of Information and Communications Technology Hokkaido University Keio University

About

Shimpei Sato is an author at Tokyo Institute of Technology specializing in engineering, computer engineering, and computer science.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	17	670
2	Computer Engineering	13	16	653
3	Computer Science	13	16	653
4	Social Sciences	1	1	82
5	Applied Physics	1	1	17

Shimpei Sato

Publications

682

Citations

H-Index

Page 1

	Year	Citations
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W Kota Ando, Kodai Ueyoshi, Kentaro Orimo, IEEE Journal of Solid-State Circuits Electrical EngineeringBinary/ternaty Neural NetworkEngineeringHardware AccelerationEnergy Efficiency	2017	154
A Lightweight YOLOv2 Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Convolutional Neural NetworkEngineeringMachine LearningRegression ProblemLightweight Yolov2	2018	133
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS Kota Ando, Kodai Ueyoshi, Kentaro Orimo, EngineeringNeural Networks (Machine Learning)Nm CmosComputer ArchitectureNeurochip	2017	82
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA Hiroki Nakahara, Tomoya Fujii, Shimpei Sato Convolutional Neural NetworkEngineeringMachine LearningHardware AlgorithmComputer Architecture	2017	71
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato Convolutional Neural NetworkEngineeringFeature DetectionMachine LearningObject Detector	2017	24
All binarized convolutional neural network and its implementation on an FPGA Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara Convolutional Neural NetworkBinarized CnnImage AnalysisMachine LearningBinarized Convolutional Circuit	2017	23
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, IEICE Transactions on Information and Systems EngineeringMachine LearningHardware AlgorithmComputer ArchitectureSoftware Engineering	2019	22
A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA Tomoya Fujii, Shimpei Sato, Hiroki Nakahara IEICE Transactions on Information and Systems Convolutional Neural NetworkEngineeringMachine LearningHardware AlgorithmComputer Architecture	2018	20
An FPGA Realization of a Random Forest with <i>k</i>-Means Clustering Using a High-Level Synthesis Design Akira Jinguji, Shimpei Sato, Hiroki Nakahara IEICE Transactions on Information and Systems Cluster ComputingEngineeringMachine LearningAdvanced ComputingHardware Algorithm	2018	20
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Convolutional Neural NetworkEngineeringMachine LearningHardware AccelerationFpga-based Training Accelerator	2019	20

Page 1