Binh Le

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology

Raul-Adrian Cernea, Long Pham, Farookh Moogat et al. · IEEE Journal of Solid-State Circuits · 2009 · 76 citations

Engineering, Computer Engineering, Computer Science +14

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Cuong Trinh, Noboru Shibata, Takumi Nakano et al. · 2009 · 69 citations

Engineering, Computer Engineering, Electrical Engineering +16

Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications

Alessandro Grossi, Elisa Vianello, Mohamed M. Sabry et al. · IEEE Transactions on Electron Devices · 2019 · 68 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Binh Le, Alessandro Grossi, Elisa Vianello et al. · IEEE Transactions on Electron Devices · 2018 · 61 citations

Engineering, Computer Engineering, Low-power Design +12

High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning

E. R. Hsieh, Massimo Giordano, B. Hodson et al. · 2019 · 54 citations

Engineering, Computer Engineering, Computer Science +10