Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Abstract

We demonstrate, for the first time, resistive RAM (RRAM) arrays where each cell can store 3 bits. Such full array-level demonstration is possible through special techniques (e.g., that exploit RRAM-specific characteristics of variations in cell resistances), presented in this paper, which efficiently allocate resistance range corresponding to each bit combination (required for proper write operation) while maintaining appropriate sensing margin (required for proper read operation). Our techniques are not restricted to 3 bits-per-cell only (and, in this paper, we demonstrate 2 bits-per-cell at the array level as well). Our measured results are based on multiple 4 Kbit arrays of 1T1R HfOx-based RRAM integrated in the back end of the line of 130-nm silicon CMOS technology. We achieve 3 bits-per-cell (2 bits-per-cell) RRAM with 11 (3) programming iterations on average.