Huan-Shun Huang

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai et al. · IEEE Journal of Solid-State Circuits · 2012 · 171 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ching-Te Chuang, Shyh‐Jye Jou et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist

Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2017 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin et al. · 2012 · 16 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Hwai‐I Yang et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2012 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +17