Narendra Devta-Prasanna

Effective and Efficient Test Pattern Generation for Small Delay Defect

Sandeep Goel, Narendra Devta-Prasanna, Ritesh Turakhia · 2009 · 46 citations

Engineering, Mem Testing, Small Delay Defects +18

On the Detectability of Scan Chain Internal Faults An Industrial Case Study

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna et al. · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2008 · 43 citations

Engineering, Inspection, Industrial Engineering +25

Detection of Internal Stuck-open Faults in Scan Chains

Fan Yang, S. Chakravarty, Narendra Devta-Prasanna et al. · 2008 · 25 citations

Engineering, Vlsi Design, Internal Stuck-open Faults +22

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007 · 18 citations

Engineering, Scan Test Cost, Mem Testing +16

Accurate measurement of small delay defect coverage of test patterns

Narendra Devta-Prasanna, Sandeep Goel, A. Gunda et al. · 2009 · 17 citations

Engineering, Measurement, Small Delay Defects +18