Effective and Efficient Test Pattern Generation for Small Delay Defect

Abstract

Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions available for testing of small delay defects result in very high pattern count and run time. In this paper, we present two effective approaches for generating timing-aware transition fault patterns that target small delay defects. We identify a subset of transition faults that should be targeted by the timing-aware ATPG; while for the rest of the faults, classic non-timing-aware transition fault patterns can be generated. Experimental results for several industrial benchmarks show that the proposed approaches result in up to 75% reduction in test pattern count compared to existing timing-aware ATPG approaches.