Hyunyoon Cho

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking

Jung‐Sik Kim, Chi Sung Oh, Hocheol Lee et al. · IEEE Journal of Solid-State Circuits · 2011 · 203 citations

Engineering, Computer Engineering, Electrical Engineering +16

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Sanguhn Cha, O Seongil, Hyunsung Shin et al. · 2017 · 76 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

Jung‐Sik Kim, Chi Sung Oh, Hocheol Lee et al. · 2011 · 43 citations

Engineering, Computer Engineering, Low-power Design +15

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee et al. · 2012 · 39 citations

Engineering, Computer Engineering, Electrical Engineering +17

28.5 A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4×128 I/Os Using TSV-Based Stacking

Jung‐Sik Kim, Hocheol Lee, Donghyuk Lee et al. · 2011 · 39 citations

Engineering, Computer Engineering, Computer Science +14