L. Dreeskornfeld - Concepedia

Author

L. Dreeskornfeld

Infineon Technologies (Germany)

Also Known As

L Dreeskornfeld, L. Dreeskornfeld, Lars Dreeskornfeld

Publications

331

Citations

H-Index

Concepts

All Affiliations

Infineon Technologies (Germany)Bielefeld University

About

L. Dreeskornfeld is an author at Infineon Technologies (Germany) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	13	14	280
2	Electrical Engineering	12	12	255
3	Applied Physics	11	11	227
4	Computer Engineering	3	3	50
5	Materials Science	2	2	25

L. Dreeskornfeld

Publications

280

Citations

H-Index

Page 1

	Year	Citations
Influence of crystal orientation and body doping on trigate transistor performance E. Landgraf, W. Rösner, M. Städele, Solid-State Electronics Electrical EngineeringEngineeringElectronic EngineeringBias Temperature InstabilityApplied Physics	2005	37
A comprehensive study of corner effects in tri-gate transistors M. Städele, R.J. Luyken, M. Roosz, Device ModelingWide-bandgap SemiconductorElectrical EngineeringEngineeringChannel Doping	2004	34
Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications Michael Specht, R. Kömmling, L. Dreeskornfeld, Non-volatile MemoryElectrical EngineeringHigh ResolutionEngineeringPhysics	2004	27
Nanoscale FinFETs for low power applications W. Rösner, E. Landgraf, Johannes Kretz, Solid-State Electronics Low-power ElectronicsElectrical EngineeringEngineeringNanoelectronicsNanocomputing	2004	23
20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices Johannes Kretz, L. Dreeskornfeld, J. Hartwich, Microelectronic Engineering Electrical EngineeringEngineeringElectron-beam LithographyBeam LithographyMicrofabrication	2003	22
Novel Dual Bit Tri-Gate Charge Trapping Memory Devices Michael Specht, R. Kömmling, F. Hofmann, IEEE Electron Device Letters Non-volatile MemoryElectrical EngineeringEngineeringNanoelectronicsDual Bit Operation	2004	19
Multi-level p+ tri-gate SONOS NAND string arrays C. Friederich, Michael Specht, Theresa Lutz, Electrical EngineeringNm Gate LengthEngineeringHigh-speed ElectronicsVlsi Design	2006	18
NVM based on FinFET device structures F. Hofmann, Michael Specht, Ulrich Dorda, Solid-State Electronics Device ModelingElectrical EngineeringEngineeringVlsi DesignMicrofabrication	2005	17
Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime R.J. Luyken, T. Schulz, J. Hartwich, Solid-State Electronics Electrical EngineeringEngineeringElectronic EngineeringSoi TransistorsApplied Physics	2003	16
Comparative study of calixarene and HSQ resist systems for the fabrication of sub-20nm MOSFET device demonstrators Johannes Kretz, L. Dreeskornfeld, G. Ilicali, Microelectronic Engineering Electrical EngineeringEngineeringNanoelectronicsApplied PhysicsSemiconductor Device Fabrication	2005	15

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