Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications

Abstract

Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.