A comprehensive study of corner effects in tri-gate transistors

Abstract

We have performed extensive 2D and 3D device simulations to assess the impact of gate and drain voltages, channel doping, discrete impurity effects, and the device dimensions on the electron density accumulation in the corner regions of tri-gate transistors. For channel doping concentrations higher than 10/sup 18/ cm/sup -3/, these 'corner effects' are found to dominate the device behavior. They are most pronounced in the subthreshold regime and significantly reduced in short devices with rounded corners, thin gate oxides, and narrow channels.