S.M. Baier

A new and simple model for GaAs heterojunction FET gate characteristics

C.-H. Chen, S.M. Baier, D.K. Arch et al. · IEEE Transactions on Electron Devices · 1988 · 78 citations

Device Modeling, Semiconductors, Electrical Engineering +10

FET Characterization using gated-TLM structure

S.M. Baier, M. S. Shur, K. Lee et al. · IEEE Transactions on Electron Devices · 1985 · 34 citations

Device Modeling, Electrical Engineering, Engineering +12

Heavy ion SEU immunity of a GaAs complementary HIGFET circuit fabricated on a low temperature grown buffer layer

Paul W. Marshall, C.J. Dale, T.R. Weatherford et al. · IEEE Transactions on Nuclear Science · 1995 · 29 citations

Lt Gaas, Dynamic Seu Characteristics, Electrical Engineering +11

Enhanced heterostructure field effect transistor CAD model suitable for simulation of mixed mode circuits

Trond Ytterdal, Tor A. Fjeldly, M. S. Shur et al. · IEEE Transactions on Electron Devices · 1999 · 25 citations

Engineering, Vlsi Design, Hfet Technologies +18

Charge-collection characteristics of GaAs heterostructure FETs fabricated with a low-temperature grown GaAs buffer layer

Dale McMorrow, T.R. Weatherford, A.R. Knudson et al. · IEEE Transactions on Nuclear Science · 1996 · 24 citations

Lt Gaas, Electrical Engineering, Engineering +11