Tae-Je Cho

Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

Heeseok Lee, YunSeok Choi, Eunseok Song et al. · 2007 · 57 citations

Engineering, Vlsi Design, Device Integration +16

Fine pitch chip interconnection technology for 3D integration

Ji-Hwan Hwang, Jongyeon. Kim, Woon‐Seong Kwon et al. · 2010 · 51 citations

3D Ic Architecture, Electrical Engineering, Chip-scale Package +15

Cost Effective 2.3D Packaging Solution by using Fanout Panel Level RDL

Joonsung Kim, Jaehoon Choi, Sanguk Kim et al. · 2021 · 29 citations

Engineering, Computer Architecture, Cost Effective 2.3D +18

Mechanisms of die and underfill cracking in flip chip PBGA package

Jongbo Shim, Eun-Chul Ahn, Tae-Je Cho et al. · 2002 · 18 citations

Materials Science, Chip-scale Package, Engineering +15

Reliability of flip chip BGA package on organic substrate

Eun-Chul Ahn, Tae-Je Cho, Ho-Joong Moon et al. · 2002 · 11 citations

Reliability, Materials Science, Reliability Engineering +13