Hung-Jen Lin

A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2016 · 124 citations

Low-power Electronics, Electrical Engineering, Cmos Platform Technology +13

Optimal testing of VLSI analog circuits

Chieh-Yuan Chao, Hung-Jen Lin, L. Miler · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1997 · 52 citations

Engineering, Analog Design, Computer Architecture +19

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M.C. Chiang, C.Y. Lin et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 49 citations

Low-power Electronics, Electrical Engineering, Cmos Platform Technology +15

Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling

Siyong Liao, T.K. Chiu, Wei-Xiang You et al. · 2023 · 47 citations

Complementary Field-effect Transistor, Electrical Engineering, Engineering +12

Modifiable vascular risk factors contribute to stroke in 1080 <i>NOTCH3</i> R544C carriers in Taiwan Biobank

Hung-Jen Lin, Chih‐Hao Chen, Ming‐Wei Su et al. · International Journal of Stroke · 2023 · 12 citations