J.A. Fifield

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

H.L. Kalter, C.H. Stapper, J. Barth et al. · IEEE Journal of Solid-State Circuits · 1990 · 114 citations

Entire Ecc Words, Engineering, Memory Design +19

High-speed on-chip ECC for synergistic fault-tolerance memory chips

J.A. Fifield, C.H. Stapper · IEEE Journal of Solid-State Circuits · 1991 · 28 citations

Engineering, Vlsi Design, Memory Design +17

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

J. Barth, D. Anand, Steven M. Burns et al. · IEEE Journal of Solid-State Circuits · 2005 · 24 citations

Non-volatile Memory, Engineering, Vlsi Design +17

High-reliability fault-tolerant 16-MBit memory chip

C.H. Stapper, J.A. Fifield, H.L. Kalter et al. · IEEE Transactions on Reliability · 1993 · 21 citations

Engineering, Computer Architecture, Integrated Circuits +20

Reliability and design qualification of a sub-micron tungsten silicide E-Fuse

W. Tonti, J.A. Fifield, J. F. Higgins et al. · 2004 · 16 citations

Engineering, Mechanical Engineering, Reliability Engineering +18