Kyung-Hoae Koo - Concepedia

Author

Kyung-Hoae Koo

Stanford University

Also Known As

Kyung-Hoae Koo

Publications

306

Citations

H-Index

Concepts

All Affiliations

Stanford University Intel (United States)Oracle (United States)

About

Kyung-Hoae Koo is an author at Stanford University specializing in computer engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	287
2	Computer Engineering	9	9	287
3	Electrical Engineering	9	9	287
4	Applied Physics	6	6	212
5	Computer Architecture	5	5	127

Kyung-Hoae Koo

Publications

287

Citations

H-Index

Page 1

	Year	Citations
Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications Kyung-Hoae Koo, Hoyeol Cho, Pawan Kapur, IEEE Transactions on Electron Devices EngineeringDevice IntegrationLatency AdvantageIntegrated CircuitsInterconnect (Integrated Circuits)	2007	92
Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies Kyung-Hoae Koo, Pawan Kapur, Krishna C. Saraswat IEEE Transactions on Electron Devices EngineeringVlsi DesignComputer ArchitectureInterconnection Network ArchitectureInterconnect (Integrated Circuits)	2009	40
5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, IEEE Journal of Solid-State Circuits Non-volatile MemorySram Array DensityEngineeringVlsi DesignMemory Design	2016	40
Performance Comparisons Between Cu/Low-$\kappa$, Carbon-Nanotube, and Optics for Future On-Chip Interconnects Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, IEEE Electron Device Letters Long WiresEngineeringFuture On-chip InterconnectsOptoelectronic DevicesIntegrated Circuits	2008	37
The Delay, Energy, and Bandwidth Comparisons between Copper, Carbon Nanotube, and Optical Interconnects for Local and Global Wiring Application Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, PhotonicsElectrical Engineering3D Ic ArchitectureOptical InterconnectsEngineering	2007	20
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology John Keane, Jaydeep P. Kulkarni, Kyung-Hoae Koo, Non-volatile MemoryEngineeringVlsi DesignComputer ArchitectureMulti-channel Memory Architecture	2016	18
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna, EngineeringComputer ArchitectureInterconnection Network ArchitectureCore Network ArchitectureHigh-performance Architecture	2010	17
Performance comparison between copper, carbon nanotube, and optical interconnects Krishna C. Saraswat, Hoyeol Cho, Pawan Kapur, Optical MaterialsEngineeringOff-chip InterconnectsComputer ArchitectureInterconnection Network Architecture	2008	12
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Optical MaterialsEngineeringDevice IntegrationInterconnect (Integrated Circuits)Wafer Scale Processing	2007	11

Page 1