L.G. Yao

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

Chenjun Ge, Cheng Lin, C.H. Ko et al. · 2004 · 109 citations

Engineering, Electrical Engineering, Low-power Design +11

Effect of polycrystalline-silicon gate types on the opposite flatband voltage shift in n-type and p-type metal–oxide–semiconductor field-effect transistors for high-k-HfO2 dielectric

Cheng Yang, Yuanxing Fang, Chia‐Hung Chen et al. · Applied Physics Letters · 2003 · 35 citations

Engineering, Electrical Engineering, Materials Science +17

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Chih-Chieh Yeh, Chih-Sheng Chang, Hong-Nien Lin et al. · 2010 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +17

Determination of deep ultrathin equivalent oxide thickness (EOT) from measuring flat-band C-V curve

Chang‐Hsiao Chen, Y.K. Fang, Ching-Fen Yang et al. · IEEE Transactions on Electron Devices · 2002 · 26 citations

Engineering, Materials Engineering, Materials Science +17

Substrate-strained silicon technology: process integration [CMOS technology]

H.C.-H. Wang, Y.-P. Wang, S.-J. Chen et al. · 2004 · 26 citations

Engineering, Electrical Engineering, Electronic Materials +15