Ashish Kumar Singh

Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

Manas Ranjan Tripathy, Ashish Kumar Singh, A Samad et al. · IEEE Transactions on Electron Devices · 2020 · 173 citations

Wide-bandgap Semiconductor, V-tfet Structure, Electrical Engineering +10

III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications

Manas Ranjan Tripathy, Ashish Kumar Singh, Kamalaksha Baral et al. · Superlattices and Microstructures · 2020 · 67 citations

Low Power Applications, Electrical Engineering, Engineering +5

TFET on Selective Buried Oxide (SELBOX) Substrate with Improved ION/IOFF Ratio and Reduced Ambipolar Current

Dhruvajyoti Barah, Ashish Kumar Singh, Brinda Bhowmick · Silicon · 2018 · 44 citations

Electrical Engineering, Engineering, Reduced Ambipolar Current +6

Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs

Sweta Chander, Srimanta Baishya, Sanjeet Kumar Sinha et al. · Superlattices and Microstructures · 2019 · 44 citations

Device Modeling, Electrical Engineering, Engineering +7

Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

Manas Ranjan Tripathy, A Samad, Ashish Kumar Singh et al. · Microelectronics Reliability · 2021 · 44 citations

Electrical Engineering, Gate Oxide, Engineering +7