Chika Tanaka

High-performance 50-nm-gate-length schottky-source/drain MOSFETs with dopant-segregation junctions

A. Kinoshita, Chika Tanaka, Ken Uchida et al. · 2005 · 47 citations

Electrical Engineering, Engineering, Electronic Engineering +9

Threshold Voltage Control by Substrate Bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX

Kensuke Ota, Masumi Saitoh, Chika Tanaka et al. · IEEE Electron Device Letters · 2013 · 28 citations

Semiconductor Technology, Electrical Engineering, Nanoscale System +13

Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Kazutaka Ikegami, Hiroshi Noguchi, C. Kamata et al. · 2014 · 28 citations

Low Power, Non-volatile Memory, Electrical Engineering +13

10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V<inf>th</inf> tunability through thin BOX

Masumi Saitoh, Kensuke Ota, Chika Tanaka et al. · 2012 · 28 citations

Semiconductors, Enhanced High-field Transport, Electrical Engineering +14

Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis

Chika Tanaka, K. Adachi, Motohiko Fujimatsu et al. · IEEE Journal of the Electron Devices Society · 2016 · 24 citations · Full text

Device Modeling, Low-power Electronics, Electrical Engineering +14