Rajiv Dunne - Concepedia

Author

Rajiv Dunne

IBM Research - Thomas J. Watson Research Center

Also Known As

R. P. Dunne, R.P. Dunne, Rajiv Dunne

Publications

792

Citations

H-Index

Concepts

All Affiliations

IBM Research - Thomas J. Watson Research Center Texas Instruments (United States)IBM (United States)IBM Research - Austin

About

Rajiv Dunne is an author at IBM Research - Thomas J. Watson Research Center specializing in electronic packaging, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	777
2	Electrical Engineering	8	8	765
3	Computer Engineering	7	7	735
4	Materials Science	2	2	42
5	Materials Engineering	1	1	30

Rajiv Dunne

Publications

777

Citations

H-Index

Page 1

	Year	Citations
When are transmission-line effects important for on-chip interconnections? A. Deutsch, G.V. Kopcsay, P.J. Restle, IEEE Transactions on Microwave Theory and Techniques Short LinesElectrical EngineeringEngineeringVlsi DesignOn-chip Interconnections	1997	382
Modeling and characterization of long on-chip interconnections for high-performance microprocessors A. Deutsch, G.V. Kopcsay, Lewis M. Terman, IBM Journal of Research and Development Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignOn-chip Interconnections	1995	174
When are transmission-line effects important for on-chip interconnections A. Deutsch, G.V. Kopcsay, P.J. Restle, Short LinesElectrical EngineeringPhysical Design (Electronics)EngineeringOn-chip Interconnections	2002	69
The importance of inductance and inductive coupling for on-chip wiring A. Deutsch, H. Smith, G. Katopis, Electrical Performance of Electronic Packaging Electrical EngineeringInductive CouplingEngineeringAdvanced Packaging (Semiconductors)Physical Design (Electronics)	2002	39
Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect Yiwei Wang, Seung‐Hyun Chae, Rajiv Dunne, EngineeringImc FormationInterconnect (Integrated Circuits)Ion ImplantationAdvanced Packaging (Semiconductors)	2012	30
Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology Rajiv Dunne, Yoshimi Takahashi, Kazuaki Mawatari, EngineeringIntegrated CircuitsPackage PlatformWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2012	28
Design guidelines for short, medium, and long on-chip interconnections A. Deutsch, Dale Becker, G. Katopis, Electrical Performance of Electronic Packaging Electrical EngineeringEngineeringAdvanced Packaging (Semiconductors)MicrofabricationComputer Architecture	2002	25
Low temperature, low profile, ultra-fine pitch copper-to-copper chip-last embedded-active interconnection technology Abhishek Choudhury, Nitesh Kumbhat, P. Markondeya Raj, Electrical EngineeringChip-scale PackageEngineeringLow ProfileAdvanced Packaging (Semiconductors)	2010	18
Measurement of impact toughness of eutectic SnPb and SnAgCu solder joints in ball grid array by mini-impact tester Yuhuan Xu, Shengquan Ou, K. N. Tu, Journal of materials research/Pratt's guide to venture capital sources Materials ScienceDamage MechanismEngineeringImpact (Mechanics)Ball Grid Array	2008	12

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