Modeling and characterization of long on-chip interconnections for high-performance microprocessors

Abstract

Long on-chip interconnections with dimensions larger than the minimum ground rules are rigorously analyzed and experimentally characterized for the first time. A test vehicle has been built and characterized with representative wiring found in high-performance CMOS microprocessor chips (line lengths of 0.8–1.6 cm, and line widths of 0.9–4.8 µm using a five-metal-layer structure). The need for distributed RLC transmission-line representation is highlighted through measured and simulated results. By showing the problems encountered when using long, nonuniform on-chip transmission lines, guidelines are developed to take advantage of the lower-resistance interconnections for use in high-speed, cycle-determining paths. Such guidelines are given both for current and optimized wiring practices and for cross-sectional structures.