Joo‐Hyung Chae - Concepedia

Author

Joo‐Hyung Chae

Seoul National University ORCID

Also Known As

J. Chae, J.‐H. Chae, Joo-Hyung Chae, Joo-hyung Chae, Joo‐Hyung Chae

Publications

410

Citations

H-Index

Concepts

All Affiliations

Seoul National University SK Group (South Korea)Kwangwoon University

About

Joo‐Hyung Chae is an author at Seoul National University specializing in computer engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	199
2	Computer Engineering	10	10	199
3	Electrical Engineering	6	6	136
4	Education	1	1	22
5	Computer Science	1	1	16

Joo‐Hyung Chae

Publications

287

Citations

H-Index

Page 1

	Year	Citations
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface Yong-Un Jeong, Hyunkyu Park, Chang‐Ho Hyun, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringNonlinear Equalization StrengthsMemory InterfaceThree-point Zq Calibration	2020	44
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator Joo‐Hyung Chae, Hyeongjun Ko, Jihwan Park, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringOscillatorsMeasurementRelaxation OscillatorQuadrature Phase Errors	2019	22
Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F<sup>2</sup> Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM Daewon Ha, Wonsok Lee, M.H. Cho,	2023	20
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces Joo‐Hyung Chae, Yong-Un Jeong, Suhwan Kim IEEE Transactions on Circuits and Systems I Regular Papers Memory InterfacesElectrical EngineeringPhase EqualizationEngineeringEnergy Efficiency	2020	19
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner Joo‐Hyung Chae, Hyeongjun Ko, Jihwan Park, IEEE Transactions on Circuits & Systems II Express Briefs EngineeringVlsi DesignClock SignalMultiplexingClock Recovery	2018	18
A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation Chang‐Ho Hyun, Hyeongjun Ko, Joo‐Hyung Chae, Low-power ElectronicsPam4 OperationElectrical EngineeringEngineeringAnalog-to-digital Converter	2019	18
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation Ji-Hyo Kang, Jaehyeok Yang, Kyunghoon Kim, IEEE Journal of Solid-State Circuits Artificial IntelligenceEngineeringVlsi DesignComputer ArchitectureMulti-channel Memory Architecture	2021	18
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface Jihwan Park, Joo‐Hyung Chae, Yong-Un Jeong, IEEE Journal of Solid-State Circuits Amplitude EmphasisElectrical EngineeringEngineeringVlsi DesignPhase Emphasis	2018	17
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces Joo‐Hyung Chae, Minchang Kim, Sungphil Choi, IEEE Transactions on Circuits & Systems II Express Briefs Weight Selection MultiplexerPull-down Tap WeightsEngineeringSingle Tap WeightMixed-signal Integrated Circuit	2019	17
25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation Kyunghoon Kim, Joo‐Hyung Chae, Jaehyeok Yang, Artificial IntelligenceEngineeringVlsi DesignGddr6 DramComputer Architecture	2021	16

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