Joo‐Hyung Chae

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

Yong-Un Jeong, Hyunkyu Park, Chang‐Ho Hyun et al. · IEEE Journal of Solid-State Circuits · 2020 · 44 citations

Electrical Engineering, Engineering, Nonlinear Equalization Strengths +12

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator

Joo‐Hyung Chae, Hyeongjun Ko, Jihwan Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019 · 22 citations

Engineering, Oscillators, Measurement +20

Highly Manufacturable, Cost-Effective, and Monolithically Stackable 4F² Single-Gated IGZO Vertical Channel Transistor (VCT) for sub-10nm DRAM

Daewon Ha, Wonsok Lee, M.H. Cho et al. · 2023 · 20 citations

Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces

Joo‐Hyung Chae, Yong-Un Jeong, Suhwan Kim · IEEE Transactions on Circuits and Systems I Regular Papers · 2020 · 19 citations

Memory Interfaces, Electrical Engineering, Phase Equalization +13

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner

Joo‐Hyung Chae, Hyeongjun Ko, Jihwan Park et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 18 citations

Engineering, Vlsi Design, Clock Signal +11