Hyeongjun Ko

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator

Joo‐Hyung Chae, Hyeongjun Ko, Jihwan Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019 · 22 citations

Engineering, Oscillators, Measurement +20

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

Hae-Kang Jung, Jaemo Yang, Jeonghun Lee et al. · 2015 · 21 citations

Electrical Engineering, Engineering, Vlsi Design +12

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner

Joo‐Hyung Chae, Hyeongjun Ko, Jihwan Park et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 18 citations

Engineering, Vlsi Design, Clock Signal +11

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation

Chang‐Ho Hyun, Hyeongjun Ko, Joo‐Hyung Chae et al. · 2019 · 18 citations

Low-power Electronics, Pam4 Operation, Electrical Engineering +14

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry

Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim et al. · 2024 · 16 citations