Hirofumi Suto

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

S. Inaba, K. Okano, Shôichi Matsuda et al. · IEEE Transactions on Electron Devices · 2002 · 75 citations

Low-power Electronics, Nitrogen Concentration, Electrical Engineering +12

Numerical Simulation on Temporal Response of Spin-Torque Oscillator to Magnetic Pulses

Kiwamu Kudo, Tazumi Nagasawa, Koichi Mizushima et al. · Applied Physics Express · 2010 · 42 citations

Engineering, Magnetic Resonance, Temporal Response +16

Nanoscale layer-selective readout of magnetization direction from a magnetic multilayer using a spin-torque oscillator

Hirofumi Suto, Tazumi Nagasawa, Kiwamu Kudo et al. · Nanotechnology · 2014 · 42 citations

Engineering, Magnetic Resonance, Novel Readout Method +20

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Nobuaki Yasutake, K. Ohuchi, M. Fujiwara et al. · 2004 · 36 citations

Low-power Electronics, Electrical Engineering, Engineering +13

Layer-Selective Switching of a Double-Layer Perpendicular Magnetic Nanodot Using Microwave Assistance

Hirofumi Suto, Tazumi Nagasawa, Kiwamu Kudo et al. · Physical Review Applied · 2016 · 34 citations

Engineering, Magnetic Resonance, Magnonics +17