C.H. Lee

A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2016 · 124 citations

Low-power Electronics, Electrical Engineering, Cmos Platform Technology +13

A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs

Y.H. Chen, Wei-Min Chan, Shau-Yu Chou et al. · 2008 · 40 citations

Low-power Electronics, Hardware Security, Electrical Engineering +13

32nm gate-first high-k/metal-gate technology for high performance low power applications

C.H. Diaz, Kenichi Gotō, H.T. Huang et al. · 2008 · 36 citations

Low-power Electronics, Electrical Engineering, Semiconductor Device +14

Impact of STI mechanical stress in highly scaled MOSFETs

Yu‐Miin Sheu, C. S. Chang, Hsin-Ying Lin et al. · 2004 · 12 citations

Engineering, Mechanical Engineering, Mechanical Stress +16

Challenges of Thin Core Substrate Flip Chip Package on Advanced Si Nodes

Christine Chiu, Kuan-Yu Chang, Jones Wang et al. · 2007 · 12 citations

Engineering, Flip Chip Package, Mechanical Engineering +17