K. Watanabe

Ultra-low on-resistance LDMOS implementation in 0.13µm CD and BiCD process technologies for analog power IC's

Koji Shirai, Koji Yonemura, K. Watanabe et al. · IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs · 2009 · 43 citations

Low-power Electronics, Electrical Engineering, Engineering +12

Safe operating area for 1200-V nonlatchup bipolar-mode MOSFET's

A. Nakagawa, Yoshio Yamaguchi, K. Watanabe et al. · IEEE Transactions on Electron Devices · 1987 · 39 citations

Electrical Engineering, Engineering, High Voltage Engineering +10

Non-latch-up 1200V 75A bipolar-mode MOSFET with large ASO

A. Nakagawa, Hiromichi Ohashi, M. Kurata et al. · 1984 · 31 citations

Electrical Engineering, Engineering, Bias Temperature Instability +3

Experimental and numerical study of non-latch-up bipolar-mode MOSFET characteristics

A. Nakagawa, Yoshio Yamaguchi, K. Watanabe et al. · 1985 · 24 citations

Device Modeling, Numerical Study, Electrical Engineering +10

A deep trench isolation integrated in a 0.13um BiCD process technology for analog power ICs

Hiroyoshi Kitahara, Tetsuya Tsukihara, Masaki Sakai et al. · 2009 · 12 citations

Low-power Electronics, Analog Power Ics, Electrical Engineering +14