Avaneesh K. Dubey

The effect of phosphorous and sulfur treatment on the surface properties of InP

R. Iyer, R. Chang, Avaneesh K. Dubey et al. · Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena · 1988 · 61 citations

Iii–v Compound Semiconductors, Engineering, Sio2 Growth +22

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

Avaneesh K. Dubey, R. K. Nagaria · Microelectronics Journal · 2018 · 55 citations

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

Avaneesh K. Dubey, R. K. Nagaria · Analog Integrated Circuits and Signal Processing · 2019 · 32 citations

Novel Latch Stage, Digital Circuit Design, Self-biased Amplification Stage +1

Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique

Avaneesh K. Dubey, R. K. Nagaria · Journal of Circuits Systems and Computers · 2018 · 19 citations

Electrical Engineering, Engineering, Circuit System +12

Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure

Rahul G. Jain, Avaneesh K. Dubey, Vikrant Varshney et al. · 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON) · 2017 · 13 citations

Engineering, Vlsi Design, Double-tail Architecture +7