Avaneesh K. Dubey - Concepedia

Author

Avaneesh K. Dubey

Motilal Nehru National Institute of Technology ORCID

Also Known As

A. Dubey, Avaneesh K. Dubey, Avaneesh Kumar Dubey

Publications

252

Citations

H-Index

Concepts

All Affiliations

Motilal Nehru National Institute of Technology

About

Avaneesh K. Dubey is an author at Motilal Nehru National Institute of Technology specializing in engineering, computer engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	5	5	115
2	Computer Engineering	4	4	54
3	Applied Physics	1	1	61
4	Chemical Engineering	1	1	61
5	Chemistry	1	1	61

Avaneesh K. Dubey

Publications

202

Citations

H-Index

Page 1

	Year	Citations
The effect of phosphorous and sulfur treatment on the surface properties of InP R. Iyer, R. Chang, Avaneesh K. Dubey, Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena Iii–v Compound SemiconductorsEngineeringSio2 GrowthOptoelectronic DevicesChemistry	1988	61
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load Avaneesh K. Dubey, R. K. Nagaria Microelectronics Journal	2018	55
Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage Avaneesh K. Dubey, R. K. Nagaria Analog Integrated Circuits and Signal Processing Novel Latch StageDigital Circuit DesignSelf-biased Amplification StageMixed-signal Integrated Circuit	2019	32
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique Avaneesh K. Dubey, R. K. Nagaria Journal of Circuits Systems and Computers Electrical EngineeringEngineeringCircuit SystemMixed-signal Integrated CircuitAnalog Design	2018	19
Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure Rahul G. Jain, Avaneesh K. Dubey, Vikrant Varshney, 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON) EngineeringVlsi DesignDouble-tail ArchitectureMixed-signal Integrated CircuitNovel Latch Structure	2017	13
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect Avaneesh K. Dubey, R. K. Nagaria Journal of Circuits Systems and Computers Low-power ElectronicsElectrical EngineeringNew DesignVlsi DesignEngineering	2018	11
Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process Vikrant Varshney, Avaneesh K. Dubey, Ankur Kumar, Low-power ElectronicsEngineeringVlsi DesignMixed-signal Integrated CircuitDynamic Comparators	2018	11

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