Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure

Abstract

Regenerative comparators due to its power efficiency and high-speed finds usage in many high-speed and low-power analog-to-digital converters. In this paper, a novel comparator based on double-tail architecture is proposed to enhance latch regeneration speed. Upon analyzing the delay expressions of some existing double-tail structures, the structure of latch stage is modified by adding cross-coupled transistors to improve latch regeneration thus enhancing comparison speed. Mathematical expression for total delay is also calculated for the proposed comparator. The proposed comparator is designed in CADENCE and simulated in SPECTRE at 90-nm CMOS technology. The simulation results indicate that for the proposed comparator energy per conversion and total delay are reduced by more than 40% and 20% respectively as compared to conventional double-tail dynamic comparator.