Pei-Yuan Chiang

A 28-nm 75-fs_rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Wanghua Wu, Chih-Wei Yao, Kunal Godbole et al. · IEEE Journal of Solid-State Circuits · 2019 · 183 citations

Pll Architecture, Integrated Phase Noise, Engineering +13

A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Wanghua Wu, Chih-Wei Yao, Chengkai Guo et al. · IEEE Journal of Solid-State Circuits · 2021 · 126 citations

Pll Architecture, Electrical Engineering, Engineering +13

A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range

Pei-Yuan Chiang, Zheng Wang, Omeed Momeni et al. · IEEE Journal of Solid-State Circuits · 2014 · 75 citations

Thz Photonics, Electrical Engineering, Engineering +14

A 200-GHz Inductively Tuned VCO With $-$7-dBm Output Power in 130-nm SiGe BiCMOS

Pei-Yuan Chiang, Omeed Momeni, Payam Heydari · IEEE Transactions on Microwave Theory and Techniques · 2013 · 69 citations

Low-power Electronics, Electrical Engineering, 7-Dbm Output Power +14

A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS

Zheng Wang, Pei-Yuan Chiang, Peyman Nazari et al. · 2013 · 65 citations

Thz Photonics, Terahertz Technology, Engineering +21